I have a simple block design which contains a custom IP with AXI interface created in IP Packager.
However, validation fails with an error similar to the following:
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /<custom_ip>_0/S_AXI(design_1_custom_ip_0_0_clk) and /microblaze_0/M_AXI_DP(design_1_clk_wiz_1_0_clk_out1)
ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
How can this be addressed?
The CLK_DOMAIN is auto-populated using the clock that is specified in the Port Maps for the signal_clock.
This clock must be the same one that is used to clock the AXI interface.
In the image above, you can see that the S_AXI is connected to the M_AXI of the interconnect; the S_AXI is being clocked by the S_AXI_ACLK, so this must be represented in the IP Interface.
To verify this: