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AR# 58245

ERROR: [Place 30-660] Global clock spines are oversubscribed. The following clock nets need to use global clock spine 28 in SLR 3: clkA and clkB.

Description


I have a large design which uses 31/32 global clock buffers and 82% LUTs on xc7v2000t.

At the Implementation stage, Vivado reports the following error:

ERROR: [Place 30-99] Placer failed with error: 'Failed to constrain global clocks sharing the same clock spine. The following clock nets need to use global clock spine 28 in SLR 3: clkA and clkB. 


How can I avoid this problem?

Solution

When more than 16 (but fewer than 32) BUFG components are required, pin selection and placement must be considered in order to avoid any possibility of contention of resources based on global clocking line contention, placement of clock loads, or both.

As in all other Xilinx 7 series FPGA devices, Clock-Capable I/O (CCIO) components and their associated Clock Management Tile (CMT) have restrictions on the BUFG components that they can drive in the SLR.

CCIO components in the top or bottom half of the SLR can drive BUFG components only in the top or bottom half of the SLR (respectively). 

Accordingly, pin and associated CMT selection must be done in a way in which no more than 16 BUFG components are required in either the top or bottom half of all SLR components collectively.

The tools automatically assign all BUFG components in a way that allows all clocks to be driven to all SLR components without contention.

 

 

AR# 58245
Date Created 11/01/2013
Last Updated 03/23/2015
Status Active
Type General Article
Devices
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.2