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AR# 58276

Vivado 2013.3 Patch for MMCME2_ADV library component

Description

This answer record provides a patch for the MMCME2_ADV library component in the Vivado 2013.3 tool release. This patch is only for the 2013.3 tool and is to be repaired in the 2013.4 tool.

This patch addresses the issue where the MMCM output clocks hold their state for several clock cycles and then return to normal operation when using the DRP functionality.

Solution

Overview

  • Date: 11/05/2013
  • File Name: AR_58276_2013_3_MMCM.zip
  • Description: Patch to correct the error with the MMCM model.
  • Answer Record: 58276
  • Platform: Windows/Linux

Instructions

Installation/Use: This patch will overwrite existing files, please make a backup copy of your original files prior to installing this patch. This patch applies only to the Vivado 2013.3 tool set. Installation and use in prior versions of Vivado are not supported.

Move the Verilog file into the source libraries:

  • The file is MMCME2_ADV.v
  • Create a copy of the existing MMCME2_ADV.v file (e.g., MMCME2_ADV.v.old)
  • Move the file to the directory: <vivado_install>/data/verilog/src/unisims/

Move the VHDL file into the source libraries:

  • The file is MMCME2_ADV.vhd
  • Create a copy of the existing MMCME2_ADV.vhd file (e.g., MMCME2_ADV.vhd.old)
  • Move the file to the directory: <vivado_install>/data/vhdl/src/unisims/primitive/

Re-run the library compilation process for all external simulation tools:

  • Example: compile_simlib -simulator ncsim -family all -language all -library all -directory ./
  • For more information on the compile_simlib command enter "help compile_simlib" on the Vivado TCL command line.

Attachments

Associated Attachments

Name File Size File Type
AR_58276_2013_3_MMCM.zip 52 KB ZIP
AR# 58276
Date Created 11/05/2013
Last Updated 11/07/2013
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.3