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AR# 58291

2013.3 - The AXI Quad SPI forces STARTUPE2 instantiation which causes a problem with AXI HWICAP


The following conflict occurs when the AXI QSPI IP and HWICAP IP are both used in a Vivado IPI design targeting a specific board (AC701, etc.):

In the AXI QSPI IP, if the Board Interface "spi flash" is selected, it will automatically instantiate the STARTUPE2 block. The AXI HWICAP IP requires either the STARTUPE2 block be instantiated, or an End Of Startup (EOS) input signal be connected.

The AXI QSPI IP does not provide an EOS output signal when the STARTUPE2 block is instantiated.

The tools will generate an error if there are two STARTUPE2 blocks in a design, as there is only one available per FPGA.


  1. Select the "spi flash" Board Interface in the AXI QSPI IP. Connect the QSPI interface in the Block design.
  2. Create the HDL wrapper file for the IPI design. Select "Copy generated wrapper to allow user edits".
  3. Deselect the "spi flash" Board Interface in the AXI QSPI IP.
  4. Deselect the STARTUPE2 block in the AXI QSPI IP.
  5. Enable the STARTUPE2 block in the HWICAP IP.
  6. Modify the HDL wrapper file to match the desired QSPI interface.
  7. Add XDC location constraints for the QSPI interface.
AR# 58291
Date Created 11/06/2013
Last Updated 08/01/2014
Status Active
Type General Article
  • Vivado Design Suite - 2013.3
  • AXI Quad SPI
  • AXI Hardware ICAP