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AR# 58292

14.7 - XPS - EMIO SD Write Protect and Card Detect Signals Not Properly Configured In Zynq FSBL


When exporting the SD interface signals for Write Protect and/or Card Detect via EMIO, the FSBL is not properly configured to reflect this routing.


To properly export the Write Protect or Card Detect signals for the SD interface, a change needs to be made to the EMIT_MASKWRITE() call found within ps7init.c.

The default call will look similar to the following (for the SDIO0 interface):

EMIT_MASKWRITE(0XF8000830, 0x003F0000U ,0x00000000U)

The first argument of this call is the address in the register space that should be updated.  The second argument is the mask of which bits should be updated.  The final argument is the value of the bits in the register space.

The complete details for the bits in the register can be found in the Zynq TRM (UG585) Register Details section.  Bits 21:16 of the register are the location of the Card Detect signal.  Bits 5:0 of the register are the location of the Write Protect signals.

To properly place the Card Detect (CD) signal at MIO pin 0 and the Write Protect (WP) signal at EMIO (eg, MIO63), the function call should be updated to:

EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000003FU)

Note: The ps7_init.c file may contain multiple calls to EMIT_MASKWRITE() for this register.  They should all be updated.

This issue only exists in EDK XPS 14.7 and earlier and is not currently planned to be fixed. It is fixed in Vivado 2013.2 and later.

AR# 58292
Date Created 11/06/2013
Last Updated 05/07/2014
Status Active
Type General Article
  • Zynq-7000
  • EDK
  • EDK - 14
  • EDK - 14.7
  • EDK - 14.6
Boards & Kits
  • Zynq-7000 All Programmable SoC Boards and Kits