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AR# 58294

Zynq-7000 AP SoC: PS SPI Controller documentation update


According to the TRM section 17.5.4, users should use SS0 when using MIO.

If an existing design does not use SS0 when using MIO pins then one of the following needs to be done to ensure proper operation of the SPI in master mode.



SPI through MIO:

  • MIO for SS0 must always be enabled. 
    If it is not used as chipselect, it needs to be tied high with a pull-up.


SPI trough EMIO:

  • SSIN is connected to EMIO and tied high in bitstream: SSIN_B=1.
    In this case for SPI to function properly:
    • PS-PL level shifters should be enabled
    • The PL should be powered on and configured
AR# 58294
Date Created 11/06/2013
Last Updated 03/23/2015
Status Active
Type General Article
  • Zynq-7000