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AR# 58349

Vivado 2013.3 - ILA - Failed to Generate Debug IP

Description

Generation of ILA debug logic sometimes fails with the following error message:

ERROR: [Chipscope 16-133] Failed to generate and synthesize debug IP "xilinx.com:ip:ila:3.0".
ERROR: [Ipptcl 7-5] XIT evaluation error: Invalid file name: c:/Users/.../AppData/Local/Temp/u_ila_0_0_CV_2-8780/u_ila_0_0_CV.srcs/sources_1/ip/u_ila_0_0_CV/u_ila_0_0_CV_ooc.xdc
ERROR: [Common 17-39] 'xit::add_ipfile' failed due to earlier errors.

Solution

This is a known issue with the 2013.3 tools and will be fixed in future versions. 

For now, it is possible to work around this error by setting one of the following environment variable tcl commands:

set ::env(TEMP) c:\\temp
or
set_param chipscope.createIpInWinTemp 0
AR# 58349
Date Created 11/11/2013
Last Updated 04/24/2014
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.3
IP
  • Integrated Logic Analyzer