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AR# 58358

2013.2 BLK_MEM_GEN_V7_3 - VHDL and Verilog simulation models are inconsistent for collision checking

Description

VHDL and Verilog simulation models are inconsistent for collision checking.

When a core is simulated with VHDL as the target language, simulation reports collision warnings while Verilog simulation will not report any such collision warnings.

Solution

This is a known issue with the Block Memory Generator core v7.3.

To work around this issue, you will need to migrate the design to the Block Memory Generator core v8.0.

This issue has been fixed in the Block Memory Generator core v8.0 included with the Vivado 2013.3 release.

AR# 58358
Date Created 11/12/2013
Last Updated 12/03/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.2
IP
  • Block Memory Generator