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AR# 58402

SRIO GEN2 v3.0 and earlier - Update to 7 Series GTX Transceiver Port RXDFEXYDEN

Description

By default, the SRIO core uses DFE mode.

For DFE mode, it is recommended to update RXDFEXYDEN to '1'. This change enhances performance for medium and long reach applications with channel losses of 15 dB or higher at the Nyquist frequency.

For more information on this change, see (Xilinx Answer 58244) Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode.

Solution

In gt_wrapper_gt_<core_name>.v/vhd, the RXDFEXYDEN port should be changed from '0' to '1'.

This will be updated in the future versions of the IP cores.


Revision History
11/22/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58244 Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode N/A N/A
AR# 58402
Date Created 11/14/2013
Last Updated 11/22/2013
Status Active
Type General Article
IP
  • Serial RapidIO