By default, the SRIO core uses DFE mode.
For DFE mode, it is recommended to update RXDFEXYDEN to '1'. This change enhances performance for medium and long reach applications with channel losses of 15 dB or higher at the Nyquist frequency.
For more information on this change, see (Xilinx Answer 58244) Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode.
In gt_wrapper_gt_<core_name>.v/vhd, the RXDFEXYDEN port should be changed from '0' to '1'.
This will be updated in the future versions of the IP cores.
11/22/2013 - Initial release