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AR# 58404

Vivado - ERROR: [Designutils 20-61] Pseudo-gates inferred from RTL source

Description

When a script is run on a design containing a black box module synthesized with Synplify Pro, the following error is seen when running the link_design command:

ERROR: [Designutils 20-61] Pseudo-gates inferred from RTL source are not valid in a structural netlist [fp_top.v:32]
ERROR: [Designutils 20-13] HDL Source containing RTL statements cannot be used to create a structural netlist

Below are the commands used:

read_verilog ./src/file1.v
read_verilog ./src/top.v
synth_design -top top -part XC7V585TFFG1761-2 -bufg 32
read_edif ./src/file1.edn
link_design -top top -part XC7V585TFFG1761-2
opt_design

Solution

The problem here is with the script. 

The link_design command is used because of the edif file, but this is not needed when an RTL project includes an edif netlist. 

Removing the link_design command removes the error. 

Here is the modified script:

read_edif ./src/file1.edn
read_verilog ./src/file1.v
read_verilog ./src/top.v
synth_design -top top -part XC7V585TFFG1761-2 -bufg 32
opt_design

AR# 58404
Date Created 11/14/2013
Last Updated 12/09/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite