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AR# 58426

Vivado 2013.3 IP Integrator, SRIO GEN2 v3.0- [Synth 8-448] named port connection 'drpclk_in' does not exist for instance 'srio_gen2_0'


I have an IPI Block Design which uses a Serial RapidIO Gen2 v3.0 IP core and contains a port "drpclk_in" that under certain configurations should be disabled.

When configuring the core, "drpclk_in" does not show up on the input side of the diagram view.
However, when I check "Show disabled ports", this port shows up, but it is not grayed out like the other disabled ports.
When the IP is placed in the Block Design, this port is shown as an input connection even though the diagram did not show it in configuration.
When I try to Synthesize the design, the following error occurs:

[Synth 8-448] named port connection 'drpclk_in' does not exist for instance 'srio_gen2_0' of module 'design_1_srio_gen2_0_0' ["test_2013_3/project_1/project_1.srcs/sources_1/bd/design_1/hdl/design_1.v":403]


To work around this issue, manually edit the generated IPI wrapper and design HDL source to remove this port.

This issue is fixed starting in Vivado 2013.4.
AR# 58426
Date 11/18/2014
Status Archive
Type General Article
  • Vivado Design Suite - 2013.3
  • Serial RapidIO
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