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AR# 58495

Xilinx PCI Express Interrupt Debugging Guide


This answer record provides the Xilinx PCI Express Interrupt Debugging Guide in a downloadable PDF to enhance its usability.

Answer records are Web-based content that are frequently updated as new information becomes available.

Please visit this answer record periodically to obtain the latest version of the PDF.


PCI Express hard blocks from Xilinx have access to three different types of interrupts: Legacy Interrupt, MSI (Message Signaled Interrupts) or MSI-X depending on their design requirements. 

This document discusses different aspects of PCI Express interrupts to successfully get interrupts working in a PCI Express design. 

Details on how to generate Legacy Interrupt and Message Signal Interrupts (MSI) can be found in the respective product guides of the Xilinx PCI Express cores.

The general principal for properly generating interrupts is same for all cores but it is slightly different in Virtex-7 FPGA Gen3 Integrated Block for PCI Express core. 

This is discussed in detail in the attached document with simulation waveforms and testbench.


Associated Attachments

Name File Size File Type
Xilinx_Answer_58495_PCIe_Interrupt_Debugging_Guide.pdf 848 KB PDF
AR# 58495
Date Created 11/21/2013
Last Updated 06/18/2014
Status Active
Type General Article
  • 7 Series Integrated Block for PCI Express (PCIe)
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)