The following error occurs when I simulate the PCIe Core v1.9 in ISE tools:
Fatal: (vsim-3363) The array length does not match the width of its verilog connection
What does it mean and how do I resolve the error?
This error typically occurs with mixed language simulation when the incorrect language library component is being selected during simulation causing a port width mismatch. This can occur on boolean signals or std_logic_vector(0:0) signals where a 1:1 mapping between VHDL and Verilog is not present. The most common cause for this error is incorrect library declaration order. In mixed language simulation, the following library order must be used:
vsim -L work -L unisims_ver -L unimacro_ver -L unisim -L unimacro -L secureip -voptargs=\"+acc\" -t 1ps glbl <filelist>
In this example, the verilog libraries are declared prior to the VHDL libararies. This is the required order for proper simulation of a mixed language design.