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AR# 58555

Vivado IP Integrator - Example IP Integrator Designs Targeting Xilinx 7 Series Demo Boards


Attached to this answer record are example IP Integrator designs targeting the Xilinx 7 series demo boards. 

These are to be used for reference purposes to explore the Vivado IP Integrator tool, or as a base design for users designs.


To use these designs, download and unzip your preferred design below, and follow the instructions in the <Example Design>.docx file.

For further documentation and guidelines in using the IP Integrator, see the Vivado Embedded Design Hardware Guide.


Associated Attachments

Name File Size File Type
KC705_2013_3.zip 8 MB ZIP
KC705_2013_2.zip 7 MB ZIP
VC707_2013_2.zip 8 MB ZIP
VC707_2013_3.zip 9 MB ZIP
VC707_2013_4.zip 4 MB ZIP
KC705_2013.4.zip 4 MB ZIP
VC707_2014.1.zip 34 MB ZIP
KC705_2014.1.zip 30 MB ZIP
VC707_2014.2.zip 28 MB ZIP
KC705_2014.2.zip 31 MB ZIP
AR# 58555
Date Created 11/26/2013
Last Updated 07/28/2014
Status Active
Type Documentation Changes
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
Boards & Kits
  • Kintex-7 FPGA KC705 Evaluation Kit