UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58562

MIG 7 Series RLDRAM3 - tWTR counter logic causes controller to lock up

Description

Version Found: v2.0 Rev1
Version Resolved: See (Xilinx Answer 54025)

In some cases, when performing a Write command followed by a Read command, the "twtr_ok" signal inside *_rld_mc.v deasserts and always remains Low. This causes the memory controller to lock up, preventing any commands from being sent to the DRAM.

Solution

This is a RTL bug found in the initialization logic of "twtr_cnt" inside the *_rld_mc.v module.

To work around the issue, the following RTL changes can be made inside *_rld_mc.v:

always @ (posedge clk)
   begin
      if (rst_clk) begin
////////////////////////////////
         twtr_cnt[0] <= #TCQ RLD_TWTR; 
         twtr_cnt[1] <= #TCQ RLD_TWTR; 
////////////////////////////////
         prev_wr_pointer_twtr <= #TCQ 'h0;
      // when 4 write requests are issued in a user clock cycle
end

Revision History
12/18/2013 - Initial release

AR# 58562
Date Created 11/26/2013
Last Updated 12/06/2013
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series