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AR# 58565

7-Series Chipscope - Timing Error in Coregen Chipscope Core When Opened in Vivado


Importing the netlists from a Chipscope core generated by 14.4 Coregen into a Vivado project can result in the following timing errors:

ERROR: [Constraints 18-513] set_false_path: list of objects specified for '-from' option contains no valid startpoints. Please check to make sure at least one valid startpoint is specified. [C:/my_demos/vivado/vivado_ila/design_files/ip_cores/my_ila.xdc:6]
INFO: [Timing 38-35] Done setting XDC timing constraints.
CRITICAL WARNING: [Timing 38-249] Generated clock U_CLK has no logical paths from master clock J_CLK.
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.

These errors are due to a missing constraint in the generated XDC file.


To work around these errors, add the following constraints to your XDC file. These examples are for a top level XDC.

set_false_path -from [get_cells 
<<instance_name>>/U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets -hier {CONTROL[0]}]] IS_CLOCK]]

set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets -hier {CONTROL[0]}]] IS_CLOCK]] -to [get_cells <<instance_name>>/U0/*/U_STAT/U_DIRTY_LDC]
set_false_path -from [get_cells <<instance_name>>/U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells <<instance_name>>/U0/*/U_STAT/U_DIRTY_LDC]

<<instance_name>> should be the ILA instance name.

The ILA instance name can be omitted if these constraints are scoped to the ILA core.

AR# 58565
Date Created 11/26/2013
Last Updated 04/28/2014
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • ChipScope ILA