We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58616

Vivado - Debugging opt_design trimming


How can I trace optimizations that occur in the sweep & propconst phases of opt_design?


Step 1
Run opt_design from the open synthesized design with all messaging enabled.

  1. Use the verbose option.

  2. Set the following parameter before running opt_design:
    set_param messaging.defaultLimit 100000
Step 2

Close the optimized design and re-open the synthesized design.

Step 3

Find a cell of interest that is being optimized (or a cell connected to a net of interest)

Step 4

Look at the messaging to find why the optimization has taken place.

If the following message is seen, trace forward to the next cell and again look at the messaging:

INFO: [Opt 31-54] Cell has no loads and is removed:

If the following message is seen, find which input has made this a constant.
If the data input of a FF is not the issue, look to make sure that the control set values are not constants .for example, R <= 1, CE <= 0 or C <= 0/1.

INFO: [Opt 31-54] Cell has no loads and is removed:

These two steps should lead you to the source of the optimizations.

You can also try using Tcl commands to find constant values for control sets.

The following example looks for FF reset ports that are connected to Vcc.

get_cells -filter {REF_NAME =~ FD*} -of_objects [get_pins -filter {REF_PIN_NAME == R} -of_objects [get_nets -hierarchical -filter {NAME =~ *const1*}]]
AR# 58616
Date Created 12/02/2013
Last Updated 03/11/2015
Status Active
Type General Article
  • Vivado Design Suite