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AR# 58634

MIG 7 Series - All VHDL designs fail VCS simulations

Description

Version Found: v2.0 Rev1
Version Resolved: See (Xilinx Answer 54025)

All MIG 7 Series VHDL designs fail simulations using VCS simulator due to a limitation with the way VCS maps VHDL generics to Verilog parameters.

Solution

This issue is scheduled to be fixed in VCS 2014.03 (Beta) and going forward.

Revision History
12/18/2013 - Initial release

AR# 58634
Date Created 12/03/2013
Last Updated 12/06/2013
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Virtex-7
  • Artix-7
IP
  • MIG 7 Series