No Phase Delay or Positive Phase Delay
In this scenario, a source-synchronous clock topology is in place and the FPGA is transmitting data to an external device. There is either no phase delay or positive phase delay added to the internal FPGA clock.
Negative Phase Delay
In this scenario, a source-synchronous clock topology is in place and the FPGA is transmitting data to an external device. There is negative phase delay added to the FPGA internal clock. Because of this negative phase delay, set_multicycle_path constraints must be added in order to analyze the correct launch and capture edges.
Note: This is a slight modification to the Language Template found in the Vivado tool (Window -> Language Templates -> XDC -> Timing Constraints -> Output Delay Constraints -> System-Synchronous -> Dual Data Rate). These templates that are shown are attached and can be downloaded from this answer record.