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AR# 58640

2013.x Vivado Timing - Constraining Outputs for a DDR System Synchronous Design

Description

How do I constrain my outputs for a System Synchronous DDR design?

Solution

No Phase Delay or Positive Phase Delay

In this scenario, a source-synchronous clock topology is in place and the FPGA is transmitting data to an external device. There is either no phase delay or positive phase delay added to the internal FPGA clock.


Negative Phase Delay

In this scenario, a source-synchronous clock topology is in place and the FPGA is transmitting data to an external device. There is negative phase delay added to the FPGA internal clock. Because of this negative phase delay, set_multicycle_path constraints must be added in order to analyze the correct launch and capture edges.


Note: This is a slight modification to the Language Template found in the Vivado tool (Window -> Language Templates -> XDC -> Timing Constraints -> Output Delay Constraints -> System-Synchronous -> Dual Data Rate). These templates that are shown are attached and can be downloaded from this answer record.

Attachments

Associated Attachments

Name File Size File Type
Sys_Sync_negative_delay.txt 2 KB TXT
Sys_Sync_nodly_or_posdly.txt 2 KB TXT
AR# 58640
Date Created 12/03/2013
Last Updated 12/10/2013
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite