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AR# 58652

LogiCORE IP Serial RapidIO v5.6 - SRL in Reset Synchronization Logic

Description

In the reset synchronization logic of the SRIO core, a LUT-based SRL16 is used.

The SRL16 is not a chain of registers, so it does not resolve metastability when it occurs.

Solution

Please find an updated "mgt_top.v" in the attachment file.

This file needs to be copied in the ISE installation folder:
<ISE_INSTALLATION_PATH>\ISE_DS\ISE\coregen\ip\xilinx\network\com\xilinx\ip\srio_v5_6\srio_phy\top
Note: You might want to first back up the old mgt_top.v file.

Then, you can generate the fixed core. The SRL has been  replaced by flipflops:


Attachments

Associated Attachments

Name File Size File Type
mgt_top.v 10 KB V
AR# 58652
Date Created 12/04/2013
Last Updated 12/06/2013
Status Active
Type General Article
IP
  • Serial RapidIO