In the 10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v3.0 (Rev. 1) core, the period for the dclk (transceiver DRP clock frequency) is over-constrained in the Out-of-Context (OOC) XDC file. A period of 6.4ns is used while the actual period is 12.8ns. This over constraint should have little to no impact. The OOC XDC file is only used for synthesis when synthesizing the core to create an individual core design checkpoint (DCP) and the constraint is not passed on to implementation. In implementation, the correct dclk period will be defined from the MMCM used to generate the clock.
This has been updated in the v3.0 (Rev. 2) patch update, see (Xilinx Answer 58658).
In v4.0 or later of the core, available in Vivado Design Suite 2013.3 or later, the update is no longer needed as the DCLK frequency has been changed to 156.25 MHz.
If using v3.0 (Rev. 1) or earlier, in the <core_name>_OOC.xdc file:
create_clock -name dclk -period 6.400 [get_ports dclk]
can be updated to:
create_clock -name dclk -period 12.800 [get_ports dclk]