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AR# 58660

10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v3.0 (Rev. 1) and earlier - Update needed to the synchronizer logic; block lock sometimes does not go High for 10GBASE-KR


If using the 10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v3.0 (Rev. 1) and earlier, there are updates that are needed to the synchronizer logic.


If using 10GBASE-R core, the synchronization logic could swallow a pulse that would result in the core sometimes missing an increment on the following counters: BER , Error Block and Test Pattern Error.


If using the 10GBASE-KR core, in addition to the described behavior for 10GBASE-R, the synchronizer logic could swallow a pulse which results in the PCS block lock state machine remaining in reset. The failure is not typically seen every time or in every implementation. If it happens, a core PMA reset has been seen to resolve the issue and allow for block lock to complete.


This issue has been fixed in the v3.0 (Rev. 2) patch update, see (Xilinx Answer 58658), and in v4.0 or later of the core available in Vivado Design Suite 2013.3 or later.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58656 10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v3.0 (Rev 2) - Downloadable Rev 2 patch update N/A N/A
AR# 58660
Date Created 12/04/2013
Last Updated 12/09/2013
Status Active
Type General Article
  • 10 Gigabit Ethernet PCS-PMA with FEC/Auto-Negotiation for backplanes (10GBASE-KR)
  • Ten Gigabit Ethernet PCS/PMA