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AR# 58671

UltraScale FPGA Transceiver Wizard v1.1 - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the UltraScale FPGA Transceiver Wizard v1.1, released with Vivado Design Suite 2013.4.

Solution

Title: Simulation support limited to QuestaSim 10.2a or Vivado Simulator.

Description: Wizard example design simulation support is limited to Mentor Graphics Questa Advanced Simulator 10.2a or Xilinx Vivado Simulator at this time.

Other simulators may be incompatible or yield inaccurate results.

Work-around: None

To Be Fixed: 2014.1

CR: 759657

Status: Resolved in 2014.1 core v1.2


Title: Use of GTY transceivers limited to behavioral simulation of the CAUI-4 preset.

Description: This release provides early, limited support of GTY transceivers in Virtex UltraScale devices.

The only available use mode at this time is behavioral simulation of CAUI-4 transceiver configuration preset.

Neither implementation of any GTY-based design, nor simulation with modifications to the CAUI-4 preset configuration are supported at this time.

Work-around: Additional GTY transceiver configurations will be available in Vivado 2014.1

To Be Fixed: 2014.1

CR: NA

Status: Resolved in 2014.1 core v1.2


Title: X propagation in netlist simulations of gearbox configurations.

Description: Post-synthesis or post-implementation netlist simulations of Wizard example design configurations which use the transceiver's RX Gearbox may time out due to X propagation caused by X's in valid RXDATA following gearbox slip operations.

This results in the simulator log message below:

"FAIL: simulation timeout. PRBS lock never achieved."

Work-around: None

To Be Fixed: 2014.1

CR: 738605

Status: Resolved in 2014.1 Software (for use with core v1.2)


Title: Unsupported programmable divider causes core generation error.

Description: Some low line rate, wide data width Wizard configurations result in the inferred use of a currently-unsupported programmable divider setting, producing the following core generation error message:

"ERROR: [xilinx.com:ip:gtwizard_ultrascale:1.0-21] <component_name>: The requested configuration requires a Programmable divider value that is not supported at this time. For your low line rate configuration, please choose narrower internal and external data widths."

Work-around: Choose narrower user and internal data width options.

To Be Fixed: Future

CR: 733011

Status: Resolved in 2014.4 core v1.4 Rev1


Title: Use of the buffer recovered clock output feature causes unroutes

Description: Enabling the buffered recovered clock output feature for MGTREFCLK1, or for any transceiver channel other than channel 0 of a given quad, results in unroutes and critical warnings similar to the following:

"CRITICAL WARNING: [Route 35-54] Net: example_wrapper_inst/<component_name>_inst/inst/rxrecclkout_out[0] is not completely routed."

Work-around: Enable the buffer recovered clock output feature for only channel 0, and choose MGTREFCLK0 as the destination buffer, for each of the desired transceiver quad(s)

To Be Fixed: 2014.1

CR: 749063

Status: Resolved in 2014.1 core v1.2


Title: Certain reference clock routing combinations can lead to routing congestion.

Description: The UltraScale serial transceiver reference clock routing architecture allows up to two northbound and two southbound reference clock nets to enter or exit any given transceiver quad.

However, the Wizard GUI does not currently enforce this limit.

When excessive north or south routing is chosen, messages similar to the following may occur during route_design:

"CRITICAL WARNING: [Route 35-162] 2 signals failed to route due to routing congestion. Please run report_route_status to get a full summary of the design's routing."

Work-around: Modify your reference clock routing selections in the Wizard GUI to limit north or south routing to the hardware capabilities

To Be Fixed: 2014.1

CR: 761346

Status: Resolved in 2014.1 core v1.2


Title: Reset controller helper block input gtwiz_reset_all_in may reset TX and RX resources in parallel.

Description:

The Wizard reset controller helper block input gtwiz_reset_all_in is designed to reset TX resources, followed by RX resources, in sequence.

An issue with bit synchronization delay variability can result in TX resources instead being reset in parallel with RX resources.

For configurations where TX must be reset before RX for stability reasons (for example, when operating in loopback), use of the following workaround is recommended.

Work-around:

Tie or drive the gtwiz_reset_all_in input low, and utilize other reset controller helper block inputs to perform the equivalent sequential reset procedure.

For example, in sequence:

1. Pulse gtwiz_reset_tx_pll_and_datapath_in

2. Wait for the rising edge of gtwiz_reset_tx_done_out

3. Pulse either:

a. gtwiz_reset_rx_datapath_in (if TX and RX data paths use the same PLL), or

b. gtwiz_reset_rx_pll_and_datapath_in (if TX and RX data paths use different PLLs)

4. Wait for the rising edge of gtwiz_reset_rx_done_out

CR: 805664

Status: Resolved in 2014.3 core v1.4


Title: Receiver termination voltage limited to FLOAT for DC coupled links.

Description: Wizard configurations which use DC link coupling must choose FLOAT for receiver termination.

This selection is available but is not currently enforced by the Wizard.

Work-around: When customizing the Wizard core instance in the GUI, select FLOAT for the Termination field in the Receiver: Advanced section of the first tab.

To Be Fixed: 2015.3

CR: 851033

Status: Resolved in 2015.3 core v1.6


Title: GTH CPLL reset disrupts TXOUTCLK in some UltraScale engineering sample devices.

Description: In GTH configurations targeting Kintex UltraScale ES1/ES2 and Virtex UltraScale ES1 engineering sample devices, resetting the CPLL will disrupt the TXOUTCLK signal, even when the CPLL is used for the RX data path and a QPLL is used for the TX data path.

This is due to the presence and operation of the CPLL calibration procedure which briefly takes control of the TXOUTCLK source during CPLL reset, irrespective of which resources the CPLL clocks.

Work-around: This behavior cannot be avoided in GTH configurations targeting the affected engineering sample devices.

If runtime disruption to TXOUTCLK in response to resetting the CPLL is not tolerable in configurations where the CPLL drives only RX resources, you will need to reset and achieve lock on the CPLL prior to, or separate from bringing up TX resources.

Note: This limitation is added to the UltraScale FPGAs Transceivers Wizard Product Guide (PG182) v1.6.

AR# 58671
Date Created 12/04/2013
Last Updated 10/16/2015
Status Active
Type Release Notes
IP
  • UltraScale FPGA Transceiver Wizard
  • IO Interfaces