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AR# 58684

Zynq-7000 Example Design - DDRC ECC Error Test (Inserting Correctable/Uncorrectable Error)

Description

When DDRC detects a correctable ECC error, it automatically corrects the error and sends back the corrected data to the bus master.

When DDRC detects an uncorrectable ECC error, it returns a SLVERR response to the bus master with the uncorrectable data. If L2 cache is disabled, CPU receives the SLVERR response directly and it causes Data Abort. If L2 cache is enabled, L2 cache reports the SLVERR by issuing an interrupt to CPU.

For both correctable and uncorrectable cases, information regarding the error (such as column, row and bank error address, error byte lane, etc.) is logged in the controller register space.

This sample test program tests the ECC error detection by inserting error bits into DDR memory.

It also provides:

  • Interrupt handler for SLVERR interrupt from L2 cache
  • Data Abort handler
  • How to check the error information in DDRC registers

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.

It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs.

Limited support is provided by Xilinx on these Example Designs.

Implementation Details
Design Type PS Only
SW Type Standalone
CPUs Single CPU @ 667MHz
PS Features DDRC, L2 Cache, GIC, OCM, UART
PL Cores None
Boards/Tools ZC706
Xilinx Tools Version Vivado 2013.3
Other details -
Files Provided
ZC706.zip

Archived Vivado project

ddrc_ecc_test.c

Source code
1_CORRECTABLE_CACHE_ON.log Serial output for correctable error test with L2 Cache enable
2_CORRECTABLE_CACHE_OFF.log Serial output for correctable error test with L2 Cache disable
3_UNCORRECTABLE_CACHE_ON.log Serial output for uncorrectable error test with L2 Cache enable
4_UNCORRECTABLE_CACHE_OFF.log Serial output for uncorrectable error test with L2 Cache disable

 

Solution

Step-by-Step Instructions:

  1. Extract zip file and open SDK workspace at ZC706/vivado20133/project_1/project_1.sdk/SDK/SDK_Export
  2. Depending on your testing, edit the macro definition at the top of ddrc_ecc_test.c.
    • Correctable error test with L2 Cache enable
    #define CORRECTABLE_CACHE_ON
    • Correctable error test with L2 Cache disable
    #define CORRECTABLE_CACHE_OFF
    • Uncorrectable error test with L2 Cache enable
    #define UN_CORRECTABLE_CACHE_ON
    • Uncorrectable error test with L2 Cache disable
    #define UN_CORRECTABLE_CACHE_OFF
  3. Run the program


Expected Results:

Check the serial output and compare with the attached log files.

Attachments

Associated Attachments

AR# 58684
Date Created 12/05/2013
Last Updated 01/31/2014
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • Vivado Design Suite - 2013.3
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC706 Evaluation Kit