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AR# 58696

IP Release Notes and Known Issues for LogiCORE UltraScale Integrated 100 Gb/s Ethernet Core for Vivado 2013.4 and Forward


This answer record contains the Release Notes and Known Issues for the LogiCORE UltraScale 100G Ethernet core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and later versions.

LogiCORE 100G Ethernet core IP Page:



General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

Core VersionVivado Tools Version
v1.4 (Rev. 1)2014.4.1

General Guidance
The table below provides Answer Records for general guidance when using the LogiCORE UltraScale Interlaken core.

Table 2: General Guidance

Article NumberArticle Title
(Xilinx Answer 55248)Vivado Timing and IP constraints
(Xilinx Answer 61626)How do I speed up simulation?
(Xilinx Answer 62457)How do I generate a license key to activate this core?

Known and Resolved Issues

The following table provides known issues for the UltraScale Interlaken core, starting with v1.0, initially released in Vivado 2013.4.

Note: The "Version Found" column lists the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 3: IP

Version Table
Article Number
Article Title Version Found Version Resolved
(Xilinx Answer 62991)Max packet length can be increased from GUI settingv1.4v1.5
(Xilinx Answer 62687)Implementation errors regarding GT placement when shared logic included in example designv1.3v1.4
(Xilinx Answer 61143)How do I generate UltraScale CMAC and Interlaken blocks in the 2014.2 release?v1.2NA
(Xilinx Answer 60158)LogiCORE 100G Ethernet v1.1 - 2014.1 Implementation results in timing errorsv1.1v1.2
(Xilinx Answer 58865)Simulation support limited to QuestaSim 10.2av1.0v1.1
(Xilinx Answer 58866)Simulation on QuestaSim 10.2a simulator takes ~4 hours to completev1.0v1.1
(Xilinx Answer 58867)Simulation on Vivado Simulator takes ~15 hours to completev1.0v1.1
(Xilinx Answer 58868)2013.4 release is restricted to simulation onlyv1.0v1.1
(Xilinx Answer 58869)100G Ethernet configuration is restricted to the CAUI-10 configuration when using GTH transceivers

Revision History:

12/18/2013Initial Release
04/07/2014Updated for 2014.1 release
06/16/2014Updated for 2014.2 release
07/25/2014Added link to AR61626

Linked Answer Records

Child Answer Records

AR# 58696
Date Created 12/05/2013
Last Updated 10/13/2016
Status Active
Type Release Notes
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2013.4
  • UltraScale - CMAC