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AR# 58718

VIVADO SIMULATOR: Can I run Timing Simulations from a VHDL project in Vivado?


I have a VHDL project in Vivado.

The UG900 User Guide states that:
"Post-Synthesis and Post-Implementation timing simulations are supported for Verilog only. There is no support for VHDL timing simulation"
Does this means I cannot run Timing Simulations in my VHDL project?

Is there any way to run Timing simulations for the project?


UG900 clarifies that there are no SIMPRIM library models for the VHDL language. As a result it is not possible to run a Timing Simulation in this language.

However, this does not mean that VHDL projects can not run Timing Simulations.

Timing simulation can be run from a Vivado VHDL project as long as you have both language licenses for the Simulator: VHDL and Verilog.

This is necessary because Vivado can only generate a Timing models Verilog netlist and for that reason a license for this language is required in the Simulator.

AR# 58718
Date 10/23/2014
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite