UG900 clarifies that there are no SIMPRIM library models for the VHDL language. As a result it is not possible to run a Timing Simulation in this language.
However, this does not mean that VHDL projects can not run Timing Simulations.
Timing simulation can be run from a Vivado VHDL project as long as you have both language licenses for the Simulator: VHDL and Verilog.
This is necessary because Vivado can only generate a Timing models Verilog netlist and for that reason a license for this language is required in the Simulator.