The generated interface will not connect properly when used in Vivado IPI 2013.2 if using an VHLS design with an array as ap_memory.
The outputs will be connected together and inputs will be tie off to zero or high impedance "Z".
This is not a Vivado HLS issue. This issue in Vivado is fixed into Vivado 2013.3 and later.
In Vivado 2013.3, the DRC will issue this critical warning:
[BD 41-237] Bus Interface property MASTER_TYPE does not match between /blk_mem_gen_3/BRAM_PORTB(BRAM_CTRL) and /mem_negate_1/data_V_PORTA(OTHER)
The warning can be either ignored or the property MASTER_TYPE changed from OTHER to BRAM_CTRL in the VHLS IP on the output interface *if* the latency of the ap_memory interface is the default value "1".
This later issue will be addressed to have the VHLS IP with the property set to BRAM_CTRL when the latency is the default value of 1.
With the issue in Vivado IPI 2013.2 the elaborated design will be:
This is the correct behavior from Vivado IPI 2013.3 and later