You can use RESOURCE directive with latency option to add latency to memory read and write, for example:
#pragma HLS RESOURCE variable=memcore=RAM_2P_BRAM latency=[number]
set_directive_resource -core RAM_2P_BRAM -latency 2 "array_RAM" mem
Where [number] = 2,3,4 etc and shows how many clock cycles are between the memory read/write address and output data.
For arrays on the top-level function interface, a latency greater than 1 allows Vivado HLS to model RAMs external to the FPGA.
For example, if the latency is set to 3, the design waits 3 clock cycles before reading data from the RAM data input port.
For internal RAMs, the following rules apply:
- If the latency is specified as 1 cycle more than the latency decided by Vivado HLS, Vivado HLS adds new output registers to the output of the operator.
- If the latency is specified as 2 more than the latency decided by Vivado HLS, Vivado HLS adds registers to the output of the operation and to the input side of the operation.
If the latency is specified as 3 or more cycles than the latency decided by Vivado HLS, Vivado HLS adds registers to the output of the operation and to the input side of the operation.
Vivado HLS automatically determines the location of any additional registers.
For more details, please refer to (UG902)