GT FIFO overflow/underflow causes no channel up in duplex.
This is observed in functional simulation of Kintex-7 FPGA cases.
This answer record provides the required updates to fix this issue.
The following updates are required for the Aurora 8B10B v10.1 or earlier core only.
These steps are required to work around a functional issue in the GT simulation model.
The updates are not required with any later versions of the Aurora 8B10B IP.
Reset the GT after FIFO overflow/underflow happens.
These changes need to be made in the <component_name>_transceiver_wrapper.v[hd] file.
1/15/2014 - Initial release
2/17/2015 - Minor updates to clarify further