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AR# 58881

Xilinx Simulation Solution Center - Design Assistant - Language Support

Description

This Answer Record contains child answer records covering Language Support for Vivado Simulator. The answer records provides explanation of these issues which you may face while using Vivado Simulator. The answer record also contains information related to known issues and good coding practices.

Note: This article is part of Xilinx Simulation Solution Center Xilinx Answer 58795. The Xilinx Simulation Solution Center is available to address all questions related to Simulation. Whether you are starting a new design with Vivado Simulator or troubleshooting a problem with a supported third party simulator, use the Xilinx Simulation Solution Center to guide you to the right information.

Solution

Simulation Language Options

(Xilinx Answer 57127) Vivado Simulator - Post Synthesis and Post Implementation Timing simulation options are greyed out in my VHDL Vivado project, how can I run VHDL timing simulations?
 
(Xilinx Answer 59598) Vivado Simulator FAQ - How do I simulate with a single language simulator?
 
(Xilinx Answer 63996) Vivado Simulation Flow - Understanding the Simulator Language Option
 

VHDL

(Xilinx Answer 62678) Does the Vivado Simulator Support VHDL 2008?
 
(Xilinx Answer 56994) Does the Vivado Simulator support the 'driving_value VHDL system task?
 
(Xilinx Answer 56237) Does the Vivado Simulator (XSim) support the 'driving attribute?
 
(Xilinx Answer 63982) Vivado Simulator (XSIM) - Language Support on VHDL
Verilog
 
(Xilinx Answer 56236) What verilog system tasks are supported in the Vivado Simulator (XSim)?
 
(Xilinx Answer 56992) Does the Vivado Simulator support the $dumpoff / $dumpon system tasks?
 
(Xilinx Answer 63983) Vivado Simulator (XSIM) - Language Support on Verilog
System Verilog
 
(Xilinx Answer 59002) 2014.x - Vivado Simulator (XSIM) - System Verilog Support
 
(Xilinx Answer 63958) 2015.1 Vivado Simulator - print format specifier %p doesn't work on associative array

 

Mixed-Language Simulation

(Xilinx Answer 64050) Vivado Simulator - Use Mixed Language Simulation

(Xilinx Answer 57549) Vivado Simulator - "[VRFC 10-1089] near character 0 ; 3 visible types match here" when directly instantiating Verilog modules in VHDL

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58796 Xilinx Simulation Solution Center - Design Assistant N/A N/A

Child Answer Records

AR# 58881
Date Created 12/18/2013
Last Updated 04/02/2015
Status Active
Type Solution Center
Tools
  • Vivado Design Suite