This Answer Record contains child answer records covering Language Support for Vivado Simulator. The answer records provides explanation of these issues which you may face while using Vivado Simulator. The answer record also contains information related to known issues and good coding practices.
Note: This article is part of Xilinx Simulation Solution Center Xilinx Answer 58795. The Xilinx Simulation Solution Center is available to address all questions related to Simulation. Whether you are starting a new design with Vivado Simulator or troubleshooting a problem with a supported third party simulator, use the Xilinx Simulation Solution Center to guide you to the right information.
Simulation Language Options
(Xilinx Answer 64050) Vivado Simulator - Use Mixed Language Simulation
(Xilinx Answer 57549) Vivado Simulator - "[VRFC 10-1089] near character 0 ; 3 visible types match here" when directly instantiating Verilog modules in VHDL