We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58928

2013.3 FIFO Generator v11.0 - Create deeper or wider FIFOs using smaller size FIFOs


FIFO Generator provides the user the ability to generate FIFOs of certain depth and width. However, there may be applications where there is a need to use deeper or wider FIFOs than what is possible with FIFO Generator.

This answer record describes a way to cascade two or more smaller FIFOs to realize larger FIFOs. Note that there is performace and resource implications to implementing larger, wider FIFOs, but this is no different from the FIFOs generated using the FIFO Generator core. The user needs to do resource/performance trade-off to ensure the implemented FIFOs meet the end application requirements.


The larger size FIFO can be created by cascading smaller FIFOs generated by the FIFO Generator core. The user needs to generate the FIFO from FIFO Generator with his configuration and then the number of FIFOs generated by the IP catalog can cascade in the different format depending upon application. There are two types of cascading possible with FIFO to increase depth and width:

  • Cascading two or more FIFOs to form a deeper FIFO
  • Building a wider FIFO by connecting two or more FIFOs in parallel

Cascading FIFOs to Increase Depth

Figure-1 shows a way of cascading N FIFO to increase depth. The application sets the first N1 FIFOs in FWFT mode and uses external resources to connect them together. The data latency of this application is the sum of the individual FIFO latencies. The maximum frequency is limited by the feedback path. The NOR gate is implemented using CLB logic.

N can be 2 or more; if N is 2, the middle FIFOs are not needed.

If WRCLK is faster than RDCLK, then INTCLK = WRCLK.

If WRCLK is equal to or slower than RDCLK, then INTCLK = RDCLK.

The ALMOST_EMPTY threshold is set in the Nth FIFO; ALMOST_FULL threshold is set in 1st FIFO.

Connecting FIFOs in Parallel to Increase Width

As shown in Figure-2, the smaller size FIFO in Depth can be connected to add width to the design. CLB logic is used to implement the AND/OR gates. All the FIFO FULL signals must be OR'ed together to create the output FULL signal, and all the FIFO EMPTY signals must be OR'ed together to create the output EMPTY signal. The maximum frequency is limited by the logic gate feedback path.

AR# 58928
Date Created 12/19/2013
Last Updated 01/22/2014
Status Active
Type General Article
  • Vivado Design Suite - 2013.3
  • FIFO Generator