We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58935

2013.4 Vivado IP Integrator - Some IP are getting duplicated in IP Integrator projects which causes issues when using revision control


If using IP Integrator designs under revision control (following the flow documented in the Vivado Design Suite User Guide (UG994), Chapter 7), it can be seen that some IP file names get changed. This is causing obvious concern when attempting to use the IPI design under revision control.

How can this issue be addressed?


There are certain IP that will be auto-generated by the Vivado tools, and if these BD files exist in the project, they are getting renamed with an increment in the file name.

The list of these IP are shown below:

  • design_name_auto_pc_* - protocol converter
  • design_name_auto_cc_* - clock converter
  • design_name_auto_us_* - width converter (upsizer)
  • design_name_auto_ds_* - width converter (downsizer)

If these IP are used in the IPI design, follow the steps below:

  1. Remove the IP mentioned above from the project.
  2. Open the Vivado project.
    • Note: It is anticipated that the user will see some critical warning messages relating to the deleted IP in Step 1 (ignore this, as these BD will be auto created).
  3. Open the Block Design
  4. Reset Output Products by right clicking on the BD file, and selecting "Reset Output Products"
  5. Generate the Bitstream
    • Note: There may be some issues in Synthesis here, relating to the removal of the auto files. This can be overcome by closing the Block Design, and re-opening again.
AR# 58935
Date 02/10/2014
Status Active
Type General Article
  • Vivado Design Suite - 2013.4
Page Bookmarked