We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58937

2015.x Vivado - Simulating IP core generated files gives: ERROR: [XSIM 43-3225] Can not find design unit work. in library work located at xsim.dir/work


I have created an IP core.

However, instead of adding the IP core .xci file to the project, I added all of the generated source files manually to the project.

When I try to simulate, Vivado fails to generate the correct compilation order for post Synthesis simulations, causing an error message similar to the following:

[XSIM 43-3225] Can not find design unit work.tb_fir_compiler_0 in library work located at xsim.dir/work.


The problem is that some files intended for "simulation only" have been added to the design source set.

For post synthesis simulation to be able to compile these files, in addition to the auto generated post synthesis simulation netlist, these "simulation only" files should be added directly to the simulation fileset.

In Vivado 2014 and 2015 it is not sufficient to leave them in the design source set and mark them as "simulation only" (Although, this is an enhancement which is being considered for a future release).

To work around this problem and run the post-synthesis Simulation, ensure that all of the sources files needed for post-synthesis simulation which are not part of the simulation netlist generated by the tool are added directly to the simulation fileset using the command below:

move_files -fileset [current_fileset -simset] [get_files <file_name>.v/vhd]

AR# 58937
Date Created 12/20/2013
Last Updated 06/10/2015
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite