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AR# 58963

2014.1 Logic Debug - How does mark_debug affect the design synthesis and implementation?

Description

How does mark_debug affect the design synthesis and implementation?

Are there any differences to the synthesis or implementation results as a result of applying or not applying this attribute in the RTL code?

Solution

Currently a net/signal with MARK_DEBUG applied automatically sets DONT_TOUCH = 1.

As a result applying mark_debug prevents any optimization on the object during Synthesis and Implementation.

Methods to remove the dependency between MARK_DEBUG and DONT_TOUCH are being investigated for a future release.
AR# 58963
Date Created 12/30/2013
Last Updated 09/04/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.2
  • More
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2014.1
  • Less