In ISE, the following period constraints are equivalent:
In Vivado, are the following create_clock constraints equivalent?
How do different startpoints of create_clock command affect the timing accuracy?
In Vivado, these two constraints are different because they are using different startpoints which define the time zero used by the Vivado IDE when computing the clock latency and uncertainty used in the slack equation.
The Vivado IDE ignores all clock tree delays coming from cells located upstream from the point at which the primary clock is defined. If you define a primary clock on a pin in the middle of the design, only part of its latency is used for timing analysis. This can be a problem if this clock communicates with other related clocks in the design, since the skew, and consequently the slack, value between the clocks can be inaccurate.