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AR# 59030

2013.4 Vivado Timing - How do different startpoints of create_clock command affect the timing accuracy?

Description

In ISE, the following period constraints are equivalent:

  1. NET "clk" TNM_NET = sys_clk;
    TIMESPEC TS_sys_clk = PERIOD "sys_clk" 10 ns HIGH 50%;

  2. NET "clk_IBUF_BUFG" TNM_NET = sys_clk;
    TIMESPEC TS_sys_clk = PERIOD "sys_clk" 10 ns HIGH 50%;

In Vivado, are the following create_clock constraints equivalent?

  1. create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
  2. create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_pins clk_IBUF_BUFG_inst/O]

How do different startpoints of create_clock command affect the timing accuracy?

Solution

Figure 1 - Clocking structure example from a clock pad through BUFG
Figure 1 - Clocking structure example from a clock pad through BUFG

In Vivado, these two constraints are different because they are using different startpoints which define the time zero used by the Vivado IDE when computing the clock latency and uncertainty used in the slack equation.

The Vivado IDE ignores all clock tree delays coming from cells located upstream from the point at which the primary clock is defined. If you define a primary clock on a pin in the middle of the design, only part of its latency is used for timing analysis. This can be a problem if this clock communicates with other related clocks in the design, since the skew, and consequently the slack, value between the clocks can be inaccurate.

AR# 59030
Date Created 01/09/2014
Last Updated 01/17/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite