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AR# 59034

FIFO structural VHDL model can behave incorrectly


When using the structural VHDL model of a FIFO Generator IP core and Vivado 2013.3 or 2013.4, it is possible that incorrect behavior may occur.

In a case that used the hard fifo (FIFO36E1), it was observed that write enable was delayed by one clock cycle and this led to incorrect data capture.


The workaround is to use a structural verilog model using the post-synthesis design checkpoint of the IP and the "write_verilog" command to create the model.

This problem is resolved in Vivado release 2014.2.

AR# 59034
Date Created 01/09/2014
Last Updated 06/05/2014
Status Active
Type General Article
  • Kintex-7
  • Virtex-7
  • Artix-7
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.4
  • FIFO Generator