This answer record covers the recommended reset sequence for the GTZ transceiver in 7 series FPGAs.
When multiple lanes are going through reset at the same time, the voltage profile drops or spikes depending on power up or power down and this can cause errors.
To avoid this, the lanes must be staggered to be reset only one lane at a time.
The attached reset sequence covers the PLL, TX and RX.
The CTLE tuning procedure is also a part of the sequence.
For designs using Vivado 2014.4 or earlier, please refer to (Xilinx Answer 63590) to generate the example code implementing the GTZ reset sequence with the new CTLE tuning sequence as recommended in this Answer Record.
This is implemented natively in the GTZ transceiver wizard released with Vivado 2015.1.
The 7 Series GTZ Advance Specification User Guide (UG478) will be updated in the next version with this new reset sequence.
Note: When implementing the new reset sequence in the FPGA as a state machine, please ensure that this is clocked with the DRP clock.
Original CTLE tuning:
02/23/2015 - Added reference to GTZ reset sequence patch update Answer Record
06/27/2014 - Added the new CTLE tuning sequence to be used only with Vivado 2014.2 or later
04/11/2014 - Updated sequence to use GTZTXRESET and GTZRXRESET.
01/20/2013 - Initial release of reset sequence utilizing TXEN/RXEN and TXRDY/RXRDY.