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AR# 59060

14.7 XPS - The Show MIO Table GUI in the Zynq MISO Configuration shows incorrect pin locations for SPI0 pins


The Show MIO Table GUI shows the SCK and MISO pins of the SPI0 peripheral on Pin 41 and Pin 40, respectively. This is incorrect.


This table is for informational purposes only.

The correct information can be located in the Zynq TRM (UG585), Table 2-4. The correct location of SCK of SPI0 is Pin 40. The correct location of MISO of SPI0 is Pin 41.

AR# 59060
Date 01/13/2014
Status Active
Type General Article
  • SoC
  • Zynq-7000
  • EDK
  • EDK - 14
  • EDK - 14.7
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