jesd204_v2_2_pselect_f.v. --> parameter [0:C_AB-1]BAR = C_BAR[0:C_AB-1];
BAR is always = 0; in Simulation,
1. C_AB is 0x7
2. C_AW is 0x7
3. CE_ADDR_SIZE = 0x7
4. C_BUS_AWIDTH = 0x9
5. TEMP_CE = 0x43
6. C_NUM_ADDRESS_RANGES = 0x1
To resolve this incorrect address, the following update should be made:
--> wire [0:C_AB-1]BAR = C_BAR[0:C_AB-1];
This change helps the simulation to work and the registers of JESD204B can now be written and read to.
This issue is only present in CoreGen ISE JESD204B designs and is not an issue with Vivado designs.
01/13/2014 - Initial Release