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AR# 59107

Zynq-7000 Example design – OCM Parity Error Test (interrupt and AXI SLVERR response)

When a parity error is detected on the OCM, an interrupt signal will be asserted to processor.

An SLVERR response can be also issued to the requesting processor, resulting in a Data Abort exception if the CPU is an A9 CPU.

This test program tests both interrupt and AXI SLVERR response for the OCM parity error.

The following behavior is expected to be processed:

When data is written into the RAM, parity is computed on each byte of the write data and written into the RAM simultaneously with the data.

The default computed parity is even but this can be changed to odd parity via an APB register field.

This OddParityEn bit is used to generate a parity error.

The software was generated by Vivado 2013.4 and tested on ZC702 production board.

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.

A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.

It's up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill their needs.

Limited support is provided by Xilinx on these Example Designs.

Step by Step Instructions:

1. In SDK 2013.4, generate a zc702 empty application, and import ocm_parity_error_test.c

2. Check the linker script, all the sections should be located to DDR.

3. Set up the terminal.

4. Run the application.

Expected Results

Interrupt/Data Abort information will be printed as below:

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Name	File Size	File Type
ocm_parity_error_test.c	6 KB	C

AR# 59107
Date	10/15/2014
Status	Active
Type	General Article
Devices	Zynq-7000
Tools	Vivado Design Suite - 2013.4
Boards & Kits	Zynq-7000 All Programmable SoC ZC702 Evaluation Kit