This Design Advisory is being released as a notification of pattern sensitivity that has been seen within the MIG 7 Series DDR3 designs.
When using aggressive data patterns (such as PRBS23), loss in the channel and skew within the silicon deteriorate the available margin.
Extensive testing has proven that enough margin deterioration occurs to limit reliable operation at maximum specified data rates.
This design advisory details the data rate limits and when additional design guidelines are recommended.
MIG 7 Series DDR3 DIMM Interfaces
Single Rank DIMM
Max data rate for single rank is 1600Mbps. Interfaces operating at or below 1600Mbps are not affected.
Dual Rank DIMM
Max data rate for dual rank is 1333Mbps. Interfaces operating at or below 1333Mbps are not affected.
MIG 7 Series DDR3 Component Interfaces
Designs using 1866Mbps components should contact Xilinx Technical Support to discuss additional recommended design guidelines.
If Vivado generates the following warning message, the information outlined in this Design Advisory applies:
10/01/2014 - Updated with 2014.3 Error Messaging
08/20/2014 - Updated Related Information
06/02/2014 - Initial Release