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AR# 59168

Vivado IP Flows - How can I determine the timing and resource utilization of an IP that has not been implemented in a design yet?


I am trying to implement an IP core or a submodule of my design by itself in order to analyze device utilization and/or timing.

The problem is that the submodule has more ports than there are I/O pins on the FPGA device I am using.

As a result, I am not able to implement the module.

Is there a way to implement this module without running into an error due to I/O pin limitations?


The suggested way to implement an IP core when the number of pins will not otherwise fit into the used device is to use the Out of Context (OOC) flow.

Add " -mode out_of_context" as an extra synthesis option.

You can then get an OOC synthesis and implementation of the whole design, and you can check the implementation results without receiving an error because you have run out of IOBs.

From the Tcl console:

set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-mode out_of_context} -objects [get_runs synth_1]

In the Vivado IDE: 

Enter the "-mode out_of_context" string under the MORE OPTIONS field of the Options tab (not the Properties tab) of the Synthesis process.

You can use the Tcl command report_utilization as follows:

  • report_utilization -cells sub_module_name
  • report_utilization -cells [get_cells sub_module_name]

AR# 59168
Date Created 01/20/2014
Last Updated 10/02/2015
Status Active
Type General Article
  • Vivado Design Suite