The timer computes the pulse width being checked using the open and close edge
arrival times and the CRPR (Clock Re-convergence Pessimism Removal).
For a given clock pin (supposing the duty cycle is 50%), the worst case high pulse width actual value is calculated in this way:
Worst case high pulse width = Close edge arrival time - Open edge arrival time - CRPR
Open edge arrival time = max clock path delay
Close edge arrival time = min clock path delay + half period
The difference between the Synthesized design and the Implemented design comes from the CRPR calculation.
In Implemented design, the NCN (Nearest Common Node) CRPR calculation is able to recognize that the common clock path of the Close edge and Open edge are completely the same.
This is because the check is on the same clock pin.
The CRPR is calculated as below:
CRPR = min clock path delay - max clock path delay
So the worst case high pulse width is finally equal to half of the period.
However, in the Synthesized design there is no support for NCN CRPR.
As a result the CRPR is under-estimated for the clock, and the high pulse width calculated in the synthesized design is smaller than half of the period (which is conservative).