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AR# 59252

Vivado Simulator 2013.4 (Patch) - Incorrect data values displayed when design contains more than 2^32 signal bits


If you use the Vivado simulator in 2013.4, the waveform will display incorrect data when the total number of signal bits in the design is greater than 2^32. This is commonly seen in designs with large memory such as 1GB DDR3.

This answer record describes a patch to the 2013.4 Vivado simulator to repair this issue.


Note: This patch requires that the Vivado Simulation TCL property TRACE_LIMIT remain set at 65536.

To verify this value is set correctly for your simulation, execute the following TCL command:

get_property TRACE_LIMIT [current_sim] 

If the TRACE_LIMIT value is not set correctly, the results of the simulation will be incorrect.

To set this value correctly, execute the following TCL command:

set_property TRACE_LIMIT 65536 [current_sim] 


File Name: AR_59252_2013.1_XSIM.zip


Patch to repair the incorrect display data when the design under simulation contains more than 2^32 signal bits. This patch is only for the Vivado 2013.4 toolset, and applies to no other versions.

Answer Record: 59252

Platform: Windows/Linux



This patch will overwrite existing files, please make a backup copy of your original files prior to installing this patch. This patch applies only to the Vivado 2013.4 tool set. Installation and use in prior versions of Vivado are not supported.

Extract the archived patch files into the following location:


Example :



Associated Attachments

Name File Size File Type
AR_59252_2013.1_XSIM.zip 13 MB ZIP
AR# 59252
Date Created 01/27/2014
Last Updated 01/31/2014
Status Active
Type General Article
  • Vivado Design Suite - 2013.4