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AR# 59257

Zynq-7000 AP SoC ZC706 Evaluation Kit PCIe Targeted Reference Design - Release Notes and Known Issues Master Answer Record

Description

This is the Release Note and Known Issues Master Answer Record for the Zynq-7000 AP SoC ZC706 Evaluation Kit PCIe Targeted Reference Design.

Solution

The Zynq-7000 AP SoC ZC706 Evaluation Kit PCIe TRD is developed on the Zynq-7000 AP SoC ZC706 Evaluation Kit. The primary components of the TRD are:

  • PCIe v2.1 compliant x4 Endpoint operating at 5 Gb/s / lane / direction
  • Bus mastering scatter-gather PCIe DMA to offload the PCIe host processor
  • Multichannel VDMA with programmable VSIZE and HSIZE
  • Multilayer display controller
  • Sobel filter
  • Java based GUI running on the PCIe host system
  • A QT based GUI running on Zynq-7000 PS
  • Xilinx PetaLinux Software Development Kit (SDK) v2013.10

Software Tools and System Requirements

Software:

  • ISE Suite Embedded Edition (see version specific information below
  • PetaLinux 2013.10 SDK
  • Proper installation of required license files for the TRD
  • Optional: ZC706 board uses CP210x USB to UART Bridge to provide COM port connection to the board. This configuration is highly recommended because the UART outputs info to hyper terminal right after power up. To use this feature, hyper terminal, Minicom, teraterm or equivalent terminal software on the host machine is required. For details, please refer to UG926 for USB-to-UART Bridge driver installation.
  • For additional information on software installation, refer to UG798 (version specific)

Hardware:

  • The reference design targets the Zynq-7000 ZC706 evaluation board, Rev B or above
  • PC with PCI Express slot (x4 PCIe v2.1 compliant, not included in the kit)
  • Fedora 16 LiveCD
  • 6 pin to 4 pin power jack
  • ZC706 evaluation board setup in the default configuration as documented in the Default Switch and Jumper Setting
  • AC power adapter (12VDC)
  • HDMI-to-HDMI or HDMI-to-DVI cable (depending on available Monitor)
  • Monitor capable of supporting 1080p60
  • USB Type-A to USB Micro-B Male cable
  • USB mouse
  • Optional: USB Type A Male to USB Mini-B Male cable if using USB-to-UART bridge
  • SD memory card reader for transferring files onto the SD card (not included in the package)

Zynq-7000 AP SoC ZC706 Evaluation Kit PCIe TRD v1.0 for ISE 14.3 with Production Silicon
  • Silicon
    • The Zynq-7000 AP Soc ZC706 Evaluation Kit ships with Production silicon. 
  • IP
    • LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
    • DMA Back End AXI model (dma_back_end_axi_model) : v0.87xd
    • 7 Series Integrated Block for PCI Express : v1.7 
    • FIFO Generator : 
    • LogiCORE IP Processing System 7 (processing_system7) : v4.02.a
    • AXI XADC Core (axi_xadc) : v1.00.a
    • AXI Interconnect (axi_interconnect) : v1.06.a
    • Clock Generator (clock_generator) : v4.03.a
    • Util Reduced Logic (util_reduced_logic) : v1.00.a
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.03.a
    • Utility Flip-Flop (util_flipflop) : v1.10.a
    • sobel_filter_top : v1.02.a
    • Compact Video Controller (logicvc) : v2.05.c
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v2.01.a
    • AXI External Slave Connector (axi_ext_slave_conn) : v1.00.a
  • Known Issues
    • Warnings: While generating (building) hardware bit stream, a message window will pop up, saying there are 5 critical warning messages.  Please ignore these warnings and press OK, to continue with the bitstream generation.
    • The logiCVC-ML and NWL DMA used in the TRD are evaluation version cores - to obtain a full license please refer to: www.xilinx.com/ipcenter/ip_license/ip_licensing_help.htm
    • The PCIe end point is not detected on a specific motherboard - reboot the machine

Zynq-7000 AP SoC ZC706 Evaluation Kit PCIe TRD v1.1 for ISE 14.4 with Production Silicon
  • Silicon
    • The Zynq-7000 AP SoC ZC706 Evaluation Kit ships with Production silicon.
  • IP
    • LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
    • DMA Back End AXI model (dma_back_end_axi_model) : v0.87xd
    • 7 Series Integrated Block for PCI Express : v1.8
    • FIFO Generator : v9.3
    • LogiCORE IP Processing System 7 (processing_system7) : v4.02.a
    • AXI XADC Core (axi_xadc) : v1.00.a
    • AXI Interconnect (axi_interconnect) : v1.06.a
    • Clock Generator (clock_generator) : v4.03.a
    • Util Reduced Logic (util_reduced_logic) : v1.00.a
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.04.a
    • Utility Flip-Flop (util_flipflop) : v1.10.a
    • sobel_filter_top : v1.04.a
    • Compact Video Controller (logicvc) : v3.00.a
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v3.00.a
    • AXI External Slave Connector (axi_ext_slave_conn) : v1.00.a
  • Known Issues
    • While generating (building) hardware bit stream, a message window will pop up, saying there are a few critical warning messages.  Please ignore these warnings and press OK, to continue with the bitstream generation.
    • The logiCVC-ML and NWL DMA used in the TRD are evaluation version cores - to obtain a full license please refer to: www.xilinx.com/ipcenter/ip_license/ip_licensing_help.htm

Zynq-7000 AP SoC ZC706 Evaluation Kit PCIe TRD v1.2 for ISE 14.5 with Production Silicon
  • Silicon
    • The Zynq-7000 AP SoC ZC706 Evaluation Kit ships with Production silicon
  • IP
    • LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
    • DMA Back End AXI model (dma_back_end_axi_model) : v0.87xd
    • 7 Series Integrated Block for PCI Express : v1.9
    • FIFO Generator : v9.3
    • LogiCORE IP Processing System 7 (processing_system7) : v4.03.a
    • AXI XADC Core (axi_xadc) : v1.00.a
    • AXI Interconnect (axi_interconnect) : v1.06.a
    • Clock Generator (clock_generator) : v4.03.a
    • Util Reduced Logic (util_reduced_logic) : v1.00.a
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.04.a
    • Utility Flip-Flop (util_flipflop) : v1.10.a
    • sobel_filter_top : v1.05.a
    • Compact Video Controller (logicvc) : v3.00.a
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v3.00.a
    • AXI External Slave Connector (axi_ext_slave_conn) : v1.00.a
    • Util Vector Logic (util_vector_logic) : v1.00.a
  • Known Issues
    • While generating (building) hardware bit stream, a message window will pop up, saying there are a few critical warning messages.  Please ignore these warnings and press OK, to continue with the bitstream generation.
    • The logiCVC- ML and NWL DMA used in the TRD are evaluation version cores - to obtain a full license please refer to: www.xilinx.com/ipcenter/ip_license/ip_licensing_help.htm

Zynq-7000 AP SoC ZC706 Evaluation Kit PCIe TRD v1.3 for ISE 14.6 with Production Silicon
  • Silicon
    • The Zynq-7000 AP SoC ZC706 Evaluation Kit ships with Production silicon
  • IP
    • LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
    • DMA Back End AXI model (dma_back_end_axi_model) : v0.87xd
    • 7 Series Integrated Block for PCI Express : v1.10
    • FIFO Generator : v9.3
    • LogiCORE IP Processing System 7 (processing_system7) : v4.03.a
    • AXI XADC Core (axi_xadc) : v1.00.a
    • AXI Interconnect (axi_interconnect) : v1.06.a
    • Clock Generator (clock_generator) : v4.03.a
    • Util Reduced Logic (util_reduced_logic) : v1.00.a
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.04.a
    • Utility Flip-Flop (util_flipflop) : v1.10.a
    • sobel_filter_top : v1.05.a
    • Compact Video Controller (logicvc) : v3.01.a
    • binary_to_grey : v1.00.a
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v3.00.a
    • AXI External Slave Connector (axi_ext_slave_conn) : v1.00.a
    • Util Vector Logic (util_vector_logic) : v1.00.a
  • Known Issues
    • While generating (building) hardware bit stream, a message window will pop up, saying there are a few critical warning messages.  Please ignore these warnings and press OK, to continue with the bitstream generation.
    • The logiCVC-ML and NWL DMA used in the TRD are evaluation version cores - to obtain a full license please refer to: www.xilinx.com/ipcenter/ip_license/ip_licensing_help.htm

Zynq-7000 AP SoC ZC706 Evaluation Kit PCIe TRD v1.4 for ISE 14.7 with Production Silicon

  • Silicon
    • The Zynq-7000 AP SoC ZC706 Evaluation Kit ships with Production silicon
  • IP
    • LogiCore IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
    • DMA Back End AXI model (dma_back_end_axi_model) : v0.87xd
    • 7 Series Integrated Block for PCI Express : v1.11
    • FIFO Generator : v9.3
    • LogiCORE IP Processing System 7 (processing_system7) : v4.03.a
    • AXI XADC Core (axi_xadc) : v1.00.a
    • AXI Interconnect (axi_interconnect) : v1.06.a
    • Clock Generator (clock_generator) : v4.03.a
    • Util Reduced Logic (util_reduced_logic) : v1.00.a
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.04.a
    • Utility Flip-Flop (util_flipflop) : v1.10.a
    • sobel_filter_top : v1.05.a
    • Compact Video Controller (logicvc) : v3.01.a
    • binary_to_grey: v1.00.a
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v3.00.a
    • AXI External Slave Connector (axi_ext_slave_conn) : v1.00.a
    • Util Vector Logic (util_vector_logic) : v1.00.a
  • Known Issues
    • While generating (building) hardware bit stream, a message window will pop up, saying there are a few critical warning messages.  Please ignore these warnings and press OK, to continue with the bitstream generation.
    • The logiCVC-ML and NWL DMA used in the TRD are evaluation version cores - to obtain a full license please refer to: www.xilinx.com/ipcentre/ip_license/ip_licensing_help.htm
AR# 59257
Date Created 01/28/2014
Last Updated 01/31/2014
Status Active
Type General Article
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC706 Evaluation Kit