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AR# 59285

Debugging Accuracy Issues between the Temperature Diode and the System Monitor/XADC

Description

In some cases, a mismatch can occur between the Die Temperature reported by the XADC/System Monitor and the value measured by an external temperature sensor using the on-chip temperature diode connected via DXP/DXN.

Solution

The temperature delta can be explained by either issues with the calibration of the External Temperature sensor and the FPGA temp diode, or issues around the setup of the XADC/System Monitor.

Take each element in isolation and check for potential sources of error.

Remote Diode

There are two key parameters that can affect the accuracy of the measurement made by the remote temperature sensor:

  • The non-ideality factor
  • Series resistance

In some cases, the temperature sensor assumes a non-ideality factor (n) of 1.

You need to consult the device data sheet to obtain the correct value for the non-ideality factor, n.

  • UltraScale Architecture: n = 1.002
  • 7 Series: n = 1.01
  • Virtex-6: n = 1.0002

It is important to rescale the output result of the remote temperature sensor using the formula below:

TACTUAL = TMEASURED(nDIODE/nSENSOR)

In terms of series resistance, roughly every ohm of series resistance will result in a ~0.5DegC error in the reported temperature.

The data sheet specs 2 ohms as a typical series resistance, so the FPGA alone can account for a certain amount of this error.

Any PCB resistance on DXP/DXN traces back to the temperature sensor will add to that.

In general, it is recommended that remote diode temperature sensing IC with series resistance cancellation be used.


UltraScale System Monitor (SYSMONE1)

System Monitor specifies temperature accuracy for both the internal and external reference:

External Reference:

  • -40C <=Tj <= 100C: +/- 4degC Accuracy
  • -55C <=Tj <= 125C: +/- 4.5degC Accuracy

Internal Reference:

  • -40C <=Tj <= 100C: +/-5degC Accuracy
  • -55C <=Tj <= 125C: +/- 6.5degC Accuracy

This accuracy is achieved once you have the following:

  • An accurate reference is being applied to it (or the internal reference is being used).
  • VCCADC is 1.8V +/-3%.
  • ADC Offset and Supply Sensor Offset and gain calibration are enabled. (Config REG1 0x41 [7:4] = 1001)
  • The ACCLK frequency is <=5.2 MHz.


To rule out the above error sources, follow these four steps:

  1. If external reference is being used, please measure VREFP relative to VREFN with DMM to ensure exactly 1.25V is being applied to the System Monitor.
  2. Measure the VCCADC to GNDADC with a DMM to ensure it is 1.8V +/-3%
  3. GNDADC should be connected to system ground via a low pass filter as per (UG580) page 71.
  4. VCCADC should have its own regulator or it can share the same regulator as VCCAUX provided it is isolated with a low pass filter, as shown on page 71 of (UG580).
  5. To discount any user design related issues with reading back results, you should use SYSMON's hardened interfaces(JTAG/I2C). Please see the attached Tcl script, AR59285_sysmone1_ultrascale.tcl. This script connects to the SYSMONE1 over JTAG in the Vivado Hardware Manager. It will check your register settings, suggest the recommended settings for the SYSMONE1, and finally it will put the system monitor into Default mode and compare the temperature and supply conversion results in default mode to the temperature and supply readings from your configuration.
  6. To ensure the right System Monitor settings are being used for calibration etc., please run the System Monitor in default mode by setting the System Monitor register 41h bits 15:12 to 0h. (The script provided can be used to do this) Alternatively, you can choose not to instantiate the SYSMON in the design and it will run in default mode and the conversion results can be read back over JTAG or I2C.
  7. Also, verify that the correct clock divide ratio is being set in register 42h of the system monitor to ensure that ADCCLK is no more than 5.2 MHz. The Tcl script provided will read the clock divide ratio and specify the max DCLK frequency allowed. This should be checked against the actual applied DCLK.
  8. To validate all of the above, SYSMON Voltage supply readings (VCCINT, VCCAUX) should be compared to Voltage Rail measurement on the PCB. This will show that the SYSMON is converting properly.


If the above has been verified, you can expect the System Monitor temperature error to be as per the datasheet.

XADC

The XADC specifies temperature accuracy as follows.

  • -40C <=Tj <= 100C: +/- 4degC Accuracy
  • -55C <=Tj <= 125C: +/- 6degC Accuracy 

This accuracy is achieved once you have the following:

  • An accurate reference is being applied.
  • VCCADC is 1.8V +/-5%.
  • Offset and gain calibration are enabled.
  • The ACCLK frequency is <=26 MHz.


To rule out the above error sources, follow these steps:

  1. If external reference is being used, please measure VREFP relative to VREFN with DMM to ensure exactly 1.25V is being applied to the XADC.
  2. Measure the VCCADC to GNDADC with a DMM to ensure it is 1.8V +/-5%.
  3. GNDADC should be connected to system ground via a low pass filter as per (UG480) page 78.
  4. VCCADC should have its own regulator or it can share the same regulator as VCCAUX provided it is isolated with a low pass filter as shown on page 78 of (UG480)
  5. To discount any user design related issues with reading back results, you should use XADC's JTAG interface. Please see the attached Tcl script, AR59285_xadc_7series.tcl. This script connects to the XADC over JTAG in the Vivado Hardware Manager. It will check your register settings, suggest the recommended settings for the XADC, finally it will put the XADC into Default mode and compare the temperature and supply conversion results in default mode to the temperature and supply readings from your configuration.
  6. To ensure that the right XADC settings are being used for calibration etc., please run the XADC in default mode by setting the XADC register 41h bits 15:12 to 0h. (The script provided can be used to do this) Alternatively, you can choose not to instantiate the XADC in the design and it will run in default mode and the conversion results can be read back over JTAG
  7. Also, verify that the correct clock divide ratio is being set in register 42h of the XADC to ensure ADCCLK is no more than 26 MHz. The Tcl script provided will read the clock divide ratio and specify the max DCLK frequency allowed. This should be checked against the actual applied DCLK.
  8. To validate all of the above XADC Voltage supply readings (VCCINT, VCCAUX) should be compared to Voltage Rail measurement on the PCB. This will show that the XADC is converting properly.


If the above has been verified, you can expect the XADC temperature error to be as per the datasheet.


Virtex-5 / Virtex-6 System Monitor

System Monitor will perform to datasheet specification if:

  • An accurate reference is being applied to it (or the internal reference is being used).
  • AVDD is 2.5V +/-5%.
  • Offset and gain calibration are enabled.
  • The ACCLK frequency is <=5.2 MHz.


To rule out the above error sources, follow these four steps:

  1. If external reference is being used, please measure VREFP relative to VREFN with DMM to ensure exactly 1.25V (2.5V for Virtex-5) is being applied to the System Monitor.
  2. Measure the AVDD to AVSS with a DMM to ensure it is 2.5V +/-5%.
  3. AVSS should be connected to system ground via a low pass filter as per (UG370) page 46.
  4. AVDD should have its own regulator or it can share the same regulator as VCCAUX provided it is isolated with a low pass filter as shown on page 46 of (UG370).
  5. To ensure that the right System Monitor settings are being used for calibration etc., please run the System Monitor in default mode by setting the System Monitor register 41h bits 13:12 to 0h.
  6. Also, verify that the correct clock divide ratio is being set in register 42h of the system monitor to ensure ADCCLK is no more than 5.2 MHz.


If the above has been verified, you can expect the System Monitor temperature error to be as per the datasheet.

Attachments

Associated Attachments

Name File Size File Type
AR59285_xadc_7series.tcl 14 KB TCL
AR59285_sysmone1_ultrascale.tcl 13 KB TCL
AR# 59285
Date Created 01/31/2014
Last Updated 03/04/2016
Status Active
Type General Article
Devices
  • Kintex-7
  • Artix-7
  • Virtex-7
  • Zynq-7000
Tools
  • Vivado Design Suite