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AR# 59288

LogiCORE DisplayPort v4.2 - Why does the PHY sometimes fail to return from reset when using the reset sequence in Figure 3-11?

Description

Why does the PHY sometimes fail to return from reset when using the reset sequence in Figure 3-11 from the DisplayPort Product Guide (PG064), December 18, 2013?

Solution

In a case which was reported, it was found that in order for the PHY to reliably return from reset, the following steps were required:

  1. Set PHY_RESET register to 0x03 (reset both CPLL and GT RX/TX).
  2. Set PHY_RESET register to 0x02 (release CPLL reset only).
  3. Wait until all lane CPLLs have locked (both bits 5:4 in PHY_STATUS register set to '1').
  4. Set PHY_RESET register to 0x00 (all resets released = inactive).
  5. Wait until also the "Reset Done" flags have activated (PHY_STATUS = 0xFF).

 

This will be updated in the next release of the LogiCORE DisplayPort Product Guide.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54522 LogiCORE IP DisplayPort - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 59288
Date Created 01/31/2014
Last Updated 05/12/2014
Status Active
Type General Article
Devices
  • Kintex-7
IP
  • DisplayPort