I connect AXI Traffic Generator to an axi_interconnect and then connect the interconnect to the Zynq PS HP0 port.
The AXI Traffic Generator is configured for High Level Traffic, DATA mode, and READ WRITE as the Transaction type.
When running simulation, the Zynq BFM does not respond to READ, so RVALID is never asserted.
I do not have a separate testbench as AXI Traffic Generator generates AXI traffic logics with this configuration.
This occurs when the PORB and SRSTB from the Zynq BFM/PS is not properly connected in simulation.
For any simulation model to work properly, it is necessary to reset it properly before starting normal transactions.
This does not happen in this case due to the missing testbench.