When a design with an IP core is synthesized or implemented, constraints from the IP core are applied to the top level design. The constraints from the core are "scoped" to the top level in order to match the correct hierarchy.
Is there any way to check what the scoped constraints of an IP end up as? The temporary xdc file seems to be wiped out at the end of a run.
I am seeing a warning indicating that an IP constraint does not match any objects. However, the object in the constraint appears to be correct. I would like to see what scoped constraint was applied to the design. Is there a way to do this?
There is no way to report the completely scoped constraints per se, however, the following ideas may be of use:
get_files -compile_order constraints -used_in synthesis