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AR# 59380

14.7 ISE Sysgen - HLS exported design blockset behaves incorrectly for vertical array mapping


I have a simple code to check array map - vertical directives for 2 arrays which gives 1 cycle mis-match between the 2 array outputs.
Also the slipped array is mis-matched with its valid signal.


This seems to be an issue with how combinatorial logic is sampled in ISE Sysgen.
Adding registers to the a and b interfaces can work around the issue.

#pragma HLS INTERFACE ap_vld register port=a
#pragma HLS INTERFACE ap_vld register port=b 

This issue can occur in ISE Sysgen but does not occur in Vivado Sysgen.

As ISE is no longer updated, please use Vivado as a work-around for 7 series devices.
AR# 59380
Date 02/18/2015
Status Active
Type General Article
  • Kintex-7
  • Artix-7
  • Virtex-7
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